1. Technical Field
The present invention generally relates to a method of manufacturing a semiconductor memory device and, more particularly, to a method of forming a buried strap for electrically connecting a storage trench capacitor to a transfer gate in a trench-capacitor type DRAM cell.
2. Description of Related Art
FIG. 1 is a circuit diagram of a conventional memory cell 10 used in a dynamic random access memory (DRAM). Memory cell 10 includes a storage capacitor 15 for storing charges and a MOS transfer transistor (or "transfer gate") 20 for controlling charge transfer. One end of the source-drain path of MOS transistor 20 is connected to bit line BL and the other end of the source-drain path of MOS transistor 20 is connected to a first electrode of capacitor 15. A second electrode of capacitor 15 is connected to a predetermined potential such as ground potential. The gate of MOS transistor 20 is connected to word line WL to which signals are applied for controlling the transfer of charges between storage capacitor 15 and bit line BL, thereby reading and writing data. While it is desirable to increase the integration density of memory cells on a memory chip by making the MOS transfer transistor and the storage capacitor smaller, the capacitor must nonetheless be large enough to store sufficient charge for ensuring that data is correctly read from and written to the memory cell. So-called trench capacitors have been developed to increase the capacitance of the storage capacitor while permitting the integration density of the memory cells to be increased.
Various techniques have been employed to connect trench capacitors to surface-located transfer gates. For example, a self-aligned buried strap as described, in Nesbit et at., A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), IEDM 93-627-630, may be used. FIGS. 2A and 2B illustrate the DRAM cell and buried strap described in the Nesbit et at. publication. Specifically, FIG. 2A illustrates a top-down view of a DRAM cell having a self-aligned buried strap and FIG. 2B is a cross-sectional view taken along line I-I' of FIG. 2A. DRAM cell 50 includes a trench capacitor 55 and a transfer gate 60. Trench capacitor 55 includes a first N+ polysilicon fill 65, a second N+ polysilicon fill 67, and a collar oxide 71. Transfer gate 60 includes N-type source/drain regions 73 and 74 formed in a P-well 75 and a polysilicon gate 77 insulatively spaced from the channel between source/drain regions 73 and 74. A bit line contact 79 electrically connects source/drain region 73 to bit line 81. A shallow trench isolation (STI) arrangement 80 electrically isolates DRAM cell 50 from an adjacent memory cell and passing word line 92. A diffusion region 83 is formed to electrically connect third polysilicon fill 69 and source/drain region 74 of MOS transfer gate 60 by outdiffusing dopants from the highly doped polysilicon fill in the storage trench into the P-well 75. Diffusion region 83 and third polysilicon fill 69 constitute a buried strap for connecting trench capacitor 55 to transfer gate 60.
However, several difficulties are associated with the buried strap concept. A first difficulty is that after the buried strap is formed, the thermal budget of the further semiconductor device fabrication process is limited. Exceeding this limit leads to an excessive outdiffusion from the trench polysilicon fill to underneath the transfer gate and towards neighboring memory cells. This dopant outdiffusion results in unacceptable changes of the transfer gate device characteristics as well as in possible electrical leakage between neighboring cells. With the shrinking design groundrule of high capacity DRAMs, the tolerable length of this outdiffusion also decreases. For example, in a 256 Mb Trench Capacitor DRAM cell with a 0.25 micrometer design groundrule and with the buried strap concept, only a 0.1 micrometer outdiffusion from the side of the trench is allowed.
Further, the limitation on the thermal budget after buried strap formation limits oxidation steps to low temperature and conflicts with the need for thermal anneals to heal implantation damage or to relieve stress built up in the silicon substrate during the fabrication process. During oxidation processes following the buried strap formation, oxygen can diffuse from the substrate surface into the collar oxide and oxidize the sidewalls of the polysilicon trench fill and the substrate as shown in FIG. 3. The collar oxide expands and forms a vertical bird's-beak-shape. This collar expansion leads to a high stress level and to generation of extended crystal defects in the substrate like dislocations and stacking faults around the most expanded part of the oxide collar. Extended crystal defects can cause electrical leakage across junctions. If the stress built up during one or several oxidation steps is below the critical level to generate crystal defects, and if there is enough thermal budget to relieve this stress by thermal anneals after the oxidation steps, the formation of extended crystal defects can be prevented. Therefore, a thermal budget which allows proper stress relief anneals is essential for a successful fabrication of a DRAM with the deep trench and buried strap concept.
Another difficulty related to the buried strap concept is the generation of extended crystal defects at the interface of polycrystalline trench fill 69 to the crystalline silicon substrate. This interface sits next to the area where the oxide collar expands most during the oxidation steps of the fabrication process and therefore is exposed to the highest stress field. During the oxidation steps, the polysilicon trench fill 69 contacting the single-crystalline silicon substrate starts to recrystallize in an uncontrolled manner over a distance which can be as far as the width of the collar oxide. Due to the inherent high stress field, crystal defects in the polysilicon grains (twins, stacking faults, etc.) act as seeds for defect formation at the interface to the neighboring substrate. Crystal defects are generated there and pushed far into the substrate.